This invention is especially useful for protecting semiconductor devices from ESD events, and especially for protecting stacked gate metal oxide semiconductor (MOS) devices formed on silicon-on-insulator (SOI) wafers. SOI technology involves the formation of transistors in a thin layer of semiconductor material (e.g., silicon) overlaying a layer of insulating material (e.g., silicon dioxide). Typically, SOI wafers have a sandwich structure with an insulating layer between two silicon layers, one on either side of the insulating layer. A typical insulating layer includes an oxide (e.g., SiO2) and is often referred to in the art as a buried oxide (BOX) layer. SOI devices have a number of advantages over devices formed on bulk silicon, including lower power consumption, higher performance and higher layout density. However, devices formed on SOI wafers are just as susceptible to ESD events as bulk silicon devices.
The silicon layer in a SOI device may initially be undoped or it may be doped uniformly with n- or p-type dopant. In either case, n- or p-type well regions are typically formed in the silicon layer by conventional photolithographic techniques. This process may be repeated to form well regions of the opposite dopant type, wherein the previously formed well regions are protected from being doped during the formation of the opposite dopant-type well regions. A portion of a well region typically forms the body of one or more MOS transistors, with the source and drain region for MOS-type transistors, for example, formed within doped areas at the surface of the well region.
A stacked gate configuration is often used in output buffers, especially when the supply voltage is at a level above the normal operating voltage of the individual MOS devices (e.g., 3.3 volt power supply with 1.8 volt devices). As shown in FIG. 1, an illustrative stacked gate semiconductor device 102 comprises an output pad 104 connected to a PMOS pull-up circuit 106 and a NMOS pull-down circuit 108. The PMOS pull-up circuit is connected to a supply voltage (VccIO) 110 for I/O pins or solder bumps, and the NMOS pull-down circuit 108 is connected to Ground (VssIO) 112. The PMOS pull-up circuit 106 includes two PMOS transistors—a first PMOS transistor (P1) 114 and a second PMOS transistor (P2) 116, each having a separate gate bias (130, 132) and gate (122, 124). The drain of P1 is coupled to the source of P2 at node 142, with the source of P1 coupled to VccIO 110; and the drain of P2 coupled to the output pad 104 through node 138. In this configuration, P2 is in series with P1, and P2 is held at a reference voltage set by the gate bias. In this way, P1 and P2 operate as a voltage divider such that under normal operating conditions neither P1 nor P2 has a voltage across it greater than the standard voltage for the MOS technology node of P1 and P2 (e.g., a typical standard voltage may be 3.3 Volts). Thus, despite a supply voltage (VccIO) of 5 V, P1 and P2 do not individually have a 5 Volt drop across them.
Similarly, the NMOS pull-down circuit 108 includes two NMOS devices, N1 120 and N2 118. The source of N1 120 is coupled to VssIO 112 and the drain of N2 118 is coupled to the output pad 104 through node 138. The drain of N1 120 is coupled to the source of N2 118 at node 144. N2 118 is held at a reference voltage by gate bias 134, and as such N1 and N2 form a voltage divider that limits the voltage across either device to levels in line with normal operating levels for each device. ESD events typically have a greater effect on the NMOS pull-down.
ESD events may take various forms, but essentially they cause a large electrostatic potential to be discharged across a device. ESD is the transient discharge of static charge, which typically arises from human handling or contact with machines. Electrostatic potentials of 4000 Volts or greater may develop on a human body. Any contact by the human body with a grounded object such as an integrated circuit (IC) pin or solder bump can result in an ESD event lasting up 100 nanoseconds (ns), with peak currents greater than 1 ampere. The energy associated with such ESD events often leads to failure of electronic devices and components. The damage is typically thermal in nature and often leads to device or interconnect burnout. Such high currents may lead to on-chip voltages that are high enough to cause oxide breakdown in thin gate MOS processes. If the gate-channel breakdown voltage of a MOS device is exceeded during an ESD event, a hole will be burned through the oxide insulator of the gate and the transistor will be destroyed.
In order to avoid damage from ESD events, preventive measures may be employed to keep an ESD event from occurring in the first place. For example, antistatic coatings may be applied to the device and human handlers may use grounding wrist straps. However, not every ESD event can be prevented. Thus, protection circuits may also be added to a device or IC chip. The problem with such protection circuits is that they use substantial layout area and raise the cost of the device.
One phenomena that affects a device's response to an ESD event is snapback. Snapback is an avalanche breakdown mechanism found in the parasitic bipolar transistors inherent in MOS-type devices. Snapback allows the parasitic bipolar transistor under the MOS devices to reduce the charge and voltage across the MOS gate structures. Snapback for non-SOI devices is well-known in the art as demonstrated in ESD in Silicon Integrated Circuits, by Ajith Amerasekera and Charvaka Duvvury (John Wiley & Sons, Ltd, 2nd ed., 2002), which is incorporated herein by reference.
None of the aforementioned techniques consistently provide effective and efficient ESD protection in SOI, and a need remains for an improved means of ESD protection in stacked gate devices formed on SOI. A good protection design would be capable of surviving an ESD event and protecting the internal transistors connected to the affected IC pin or solder bump. In addition, such protection would not expand the required layout area for the device, nor would it add to the cost of manufacturing the device.